MC68HC908GZ8 Datasheet, PDF (315/344 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
23.9 I/O Registers
NOTE:
References to either timer 1 or timer 2 may be made in the following text by omitting
the timer number. For example, TSC may generically refer to both T1SC AND
T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
23.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
6
5
4
3
Read: TOF
Write:
0
TOIE
TSTOP
0
TRST
0
Reset:
0
0
1
0
0
= Unimplemented
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 23-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. Clear TOF by reading the TIM
status and control register when TOF is set and then writing a logic 0 to TOF. If
another TIM overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot
be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a
logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
MC68HC908GZ8
Freescale Semiconductor
Timer Interface Module (TIM)
Data Sheet
315