MC68HC908GZ8 Datasheet, PDF (258/344 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
OSC2
OSC1
OSCILLATOR (OSC)
OSCENINSTOP
FROM
CONFIG
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMOUT
TO TBM,TIM1,TIM2, ADC, MSCAN
SIM
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
TO MSCAN
Figure 20-3. System Clock Signals
20.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to
clock the SIM counter. The CPU and peripheral clocks do not become active until
after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK
cycles. See 20.6.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of
clocks for other modules. Refer to the wait mode subsection of each module to see
if the module is active or inactive in wait mode. Some modules can be programmed
to be active in wait mode.
20.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
• Forced monitor mode entry reset (MODRST)
Data Sheet
258
System Integration Module (SIM)
MC68HC908GZ8
Freescale Semiconductor