MC68HC908GZ8 Datasheet, PDF (236/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
NOTE:
ENSCI — Enable ESCI Bit
This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing
ENSCI sets the SCTE and TC bits in ESCI status register 1 and disables
transmitter interrupts. Reset clears the ENSCI bit.
1 = ESCI enabled
0 = ESCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the
TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
Setting the TXINV bit inverts all transmitted values including idle, break, start, and
stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether ESCI characters are eight or nine bits
long (See Table 19-5).The ninth bit can serve as a receiver wakeup signal or as
a parity bit. Reset clears the M bit.
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
Table 19-5. Character Format Selection
Control Bits
M
PEN:PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Start
Bits
1
1
1
1
1
1
Data
Bits
8
9
7
7
8
8
Character Format
Parity
Stop
Bits
None
1
None
1
Even
1
Odd
1
Even
1
Odd
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the ESCI: a logic 1
(address mark) in the MSB position of a received character or an idle condition
on the RxD pin. Reset clears the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the ESCI starts counting logic 1s as idle
character bits. The counting begins either after the start bit or after the stop bit.
If the count begins after the start bit, then a string of logic 1s preceding the stop
Data Sheet
236
Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ8
Freescale Semiconductor