MC68HC908GZ8 Datasheet, PDF (42/344 Pages) Motorola, Inc – Microcontrollers

Low-Power Modes
3.3 Break Module (BRK)
3.3.1 Wait Mode
If enabled, the break (BRK) module is active in wait mode. In the break routine, the
user can subtract one from the return address on the stack if the SBSW bit in the
break status register is set.
3.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect
break module register states.
3.4 Clock Generator Module (CGM)
3.4.1 Wait Mode
The clock generator module (CGM) remains active in wait mode. Before entering
wait mode, software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive applications
can disengage the PLL without turning it off. Applications that require the PLL to
wake the MCU from wait mode also can deselect the PLL output without turning off
the PLL.
3.4.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP
instruction disables the CGM (oscillator and phase-locked loop) and holds low all
CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two
driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control
register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as
the source of CGMOUT. When the MCU recovers from STOP, the crystal clock
divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop
is shut off, but the oscillator will continue to operate in stop mode.
3.5 Computer Operating Properly Module (COP)
3.5.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at
COP timeout.
Data Sheet
42
Low-Power Modes
MC68HC908GZ8
Freescale Semiconductor