MC68HC908GZ8 Datasheet, PDF (34/344 Pages) Motorola, Inc – Microcontrollers

Memory Map
Addr.
$0017
$0018
$0019
$001A
Register Name
Bit 7
ESCI Status Register 2 ^Read:
(SCS2) Write:
See page 243. _Reset:
0
ESCI Data Register ^{Read: R7}
(SCDR) Write: T7
See page 244. _Reset:
ESCI Baud Rate Register ^Read: _LINT
(SCBR) Write:
See page 244. _Reset:
0
Keyboard Status Read: 0
and Control Register
(INTKBSCR)
Write:
See page 143. ^Reset:
0
6
5
4
3
2
1
Bit 0
BKF
RPF
0
0
0
0
0
0
0
R6
R5
R4
R3
R2
R1
R0
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
LINR
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
0
0
0
0
KEYF
0
IMASKK MODEK
ACKK
0
0
0
0
0
0
0
$001B
Keyboard Interrupt Enable ^Read:
Register (INTKBIER) Write:
See page 144. _Reset:
KBIE7
0
KBIE6
0
KBIE5
0
KBIE4
0
KBIE3
0
KBIE2
0
KBIE1
0
KBIE0
0
$001C
Timebase Module Control ^{Read: TBIF}
Register (TBCR) Write:
TBR2
TBR1
TBR0
0
TACK
TBIE
TBON
R
See page 302. _Reset:
0
0
0
0
0
0
0
0
$001D
IRQ Status and Control ^Read:
0
Register (INTSCR) Write:
0
0
0
IRQF1
0
ACK1
IMASK1 MODE1
See page 138. _Reset:
0
0
0
0
0
0
0
0
$001E
Configuration Register 2 Read: 0
(CONFIG2)⁽¹⁾
See page 104.
Write:
0
0
0
MSCAN-E
N
TMCLKSEL
OSCENIN-
STOP
SCIBDSRC
Reset: 0
0
0
0
0
0
0
1
$001F
Configuration Register 1 ^Read:
(CONFIG1)⁽¹⁾ Write:
See page 104. _Reset:
COPRS
0
LVISTOP
0
LVIRSTD
0
LVIPWRD
0
LVI5OR3
(Note 1)
0
SSREC
0
STOP
0
COPD
0
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Timer 1 Status and Control ^{Read: TOF}
$0020
Register (T1SC) Write: 0
0
TOIE
TSTOP
TRST
0
See page 315. _Reset:
0
0
1
0
0
Timer 1 Counter ^{Read: Bit 15}
14
13
12
11
$0021 Register High (T1CNTH) Write:
See page 317. _Reset:
0
0
0
0
0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Data Sheet
34
Memory Map
MC68HC908GZ8
Freescale Semiconductor