MC68HC908GZ8 Datasheet, PDF (244/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time
period of the start bit search. RPF does not generate an interrupt request. RPF
is reset after the receiver detects false start bits (usually from noise or a baud
rate mismatch), or when the receiver detects an idle character. Polling RPF
before disabling the ESCI module or entering stop mode can show whether a
reception is in progress.
1 = Reception in progress
0 = No reception in progress
19.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the ESCI data
register.
Address: $0018
Bit 7
6
Read: R7
R6
Write: T7
T6
Reset:
5
4
3
2
R5
R4
R3
R2
T5
T4
T3
T2
Unaffected by reset
1
Bit 0
R1
R0
T1
T0
Figure 19-15. ESCI Data Register (SCDR)
NOTE:
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits, R7:R0.
Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no
effect on the ESCI data register.
Do not use read-modify-write instructions on the ESCI data register.
19.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register
selects the baud rate for both the receiver and the transmitter.
NOTE: There are two prescalers available to adjust the baud rate. One in the ESCI baud
rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
LINT
LINR
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 19-16. ESCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
Data Sheet
244
Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ8
Freescale Semiconductor