MC68HC908GZ8 Datasheet, PDF (288/344 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate
transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate
receiver CPU interrupt requests, regardless of the state of the SPE bit. See Figure
21-11.
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to
generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set
so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error
CPU interrupt requests.
SPTE SPTIE SPE
NOT AVAILABLE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
DMAS
SPRIE SPRF
NOT AVAILABLE
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 21-11. SPI Interrupt Request Generation
The following sources in the SPI status and control register can generate CPU
interrupt requests:
• SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte
transfers from the shift register to the receive data register. If the SPI
receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI
receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a
byte transfers from the transmit data register to the shift register. If the SPI
transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE
CPU interrupt request.
Data Sheet
288
Serial Peripheral Interface (SPI) Module
MC68HC908GZ8
Freescale Semiconductor