MC68HC908GZ8 Datasheet, PDF (293/344 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
I/O Registers
21.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the
port output buffers. It is internally connected to V_SS as shown in Table 21-1.
21.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
21.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Bit 7
Read:
Write:
SPRIE
Reset:
0
R
6
5
R
SPMSTR
0
1
= Reserved
4
CPOL
0
3
2
1
CPHA SPWOM SPE
1
0
0
= Unimplemented
Figure 21-13. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit.
The SPRF bit is set when a byte transfers from the shift register to the receive
data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
MC68HC908GZ8
Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
Data Sheet
293