MC68HC908GZ8 Datasheet, PDF (73/344 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
5.8.2 ADC Data Register High and Data Register Low
5.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the
10-bit result. The only difference from left justified mode is that the AD9 is
complemented. The ADRL register holds the two LSBs of the 10-bit result. All other
bits read as 0. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D
Bit 7
6
5
4
3
2
Read: AD9
AD8
AD7
AD6
AD5
AD4
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD1
AD0
0
0
0
0
Write:
Reset:
Unaffected by reset
= Unimplemented
ADRH
1
Bit 0
AD3
AD2
ADRL
0
0
Figure 5-4. ADC Data Register High (ADRH) and Low (ADRL)
5.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the
10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the
10-bit result. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D
Bit 7
6
5
4
3
2
Read:
0
0
0
0
0
0
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
= Unimplemented
ADRH
1
Bit 0
AD9
AD8
ADRL
AD1
AD0
Figure 5-5. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ8
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Data Sheet
73