MC68HC908GZ8 Datasheet, PDF (250/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
19.9 ESCI Arbiter
The ESCI module comprises an arbiter module designed to support software for
communication tasks as bus arbitration, baud rate recovery and break time
detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and
control logic. The CPU can control operation mode via the ESCI arbiter control
register (SCIACTL).
19.9.1 ESCI Arbiter Control Register
Address: $000A
Bit 7
Read: _AM1
Write:
Reset:
0
6
5
ALOST
AM0
0
0
= Unimplemented
4
ACLK
0
3
2
1
AFIN
ARUN AROVFL
0
0
0
Figure 19-18. ESCI Arbiter Control Register (SCIACTL)
Bit 0
ARD8
0
AM1 and AM0 — Arbiter Mode Select Bits
These read/write bits select the mode of the arbiter module as shown in Table
19-13. Reset clears AM1 and AM0.
Table 19-13. ESCI Arbiter Selectable Modes
AM[1:0]
00
01
10
11
ESCI Arbiter Mode
Idle / counter reset
Bit time measurement
Bus arbitration
Reserved / do not use
ALOST — Arbitration Lost Flag
This read-only bit indicates loss of arbitration. Clear ALOST by writing a logic 0
to AM1. Reset clears ALOST.
ACLK — Arbiter Counter Clock Select Bit
This read/write bit selects the arbiter counter clock source.
Reset clears ACLK.
1 = Arbiter counter is clocked with one half of the ESCI input clock generated
by the ESCI prescaler
0 = Arbiter counter is clocked with one half of the bus clock
AFIN— Arbiter Bit Time Measurement Finish Flag
This read-only bit indicates bit time measurement has finished. Clear AFIN by
writing any value to SCIACTL. Reset clears AFIN.
1 = Bit time measurement has finished
0 = Bit time measurement not yet finished
Data Sheet
250
Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ8
Freescale Semiconductor