MC68HC908GZ8 Datasheet, PDF (237/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
I/O Registers
NOTE:
bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly
synchronized transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the ESCI parity function (see Table 19-5). When
enabled, the parity function inserts a parity bit in the MSB position (see Table
19-3). Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the ESCI generates and checks for odd
parity or even parity (see Table 19-5). Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
Changing the PTY bit in the middle of a transmission or reception can generate a
parity error.
19.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
• Enables these CPU interrupt requests:
– SCTE bit to generate transmitter CPU interrupt requests
– TC bit to generate transmitter CPU interrupt requests
– SCRF bit to generate receiver CPU interrupt requests
– IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables ESCI wakeup
• Transmits ESCI break characters
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read: _SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 19-10. ESCI Control Register 2 (SCC2)
MC68HC908GZ8
Freescale Semiconductor
Enhanced Serial Communications Interface (ESCI) Module
Data Sheet
237