MC68HC908GZ8 Datasheet, PDF (239/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
I/O Registers
NOTE:
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver
interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input
or an address mark brings the receiver out of the standby state and clears the
RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed
by a logic 1. The logic 1 after the break character guarantees recognition of a
valid start bit. If SBK remains set, the transmitter continuously transmits break
characters with no logic 1s between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK
before the preamble begins causes the ESCI to send a break character instead of
a preamble.
19.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
• Stores the ninth ESCI data bit received and the ninth ESCI data bit to be
transmitted.
• Enables these interrupts:
– Receiver overrun
– Noise error
– Framing error
– Parity error
Address:
Read:
Write:
Reset:
$0015
Bit 7
R8
U
6
5
T8
R
0
0
= Unimplemented
4
3
2
1
Bit 0
R
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
R
= Reserved U = Unaffected
Figure 19-11. ESCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8)
of the received character. R8 is received at the same time that the SCDR
receives the other 8 bits.
MC68HC908GZ8
Freescale Semiconductor
Enhanced Serial Communications Interface (ESCI) Module
Data Sheet
239