MC68HC908GZ8 Datasheet, PDF (87/344 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Functional Description
depending on the application. (See 7.6 Interrupts for information and precautions
on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control
mode:
• The ACQ bit (See 7.5.2 PLL Bandwidth Control Register.) is a read-only
indicator of the mode of the filter. (See 7.3.4 Acquisition and Tracking
Modes.)
• The ACQ bit is set when the VCO frequency is within a certain tolerance and
is cleared when the VCO frequency is out of a certain tolerance. (See 7.8
Acquisition/Lock Time Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance
and is cleared when the VCO frequency is out of a certain tolerance. (See
7.8 Acquisition/Lock Time Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock
condition changes, toggling the LOCK bit. (See 7.5.1 PLL Control
Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by
systems that do not require an indicator of the lock condition for proper operation.
Such systems typically operate well below f_BUSMAX.
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before
turning on the PLL in manual mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time,
t_ACQ (See 7.8 Acquisition/Lock Time Specifications.), after turning on the
PLL by setting PLLON in the PLL control register (PCTL).
• Software must wait a given time, t_AL, after entering tracking mode before
selecting the PLL as the clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
MC68HC908GZ8
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
87