MC68HC908GZ8 Datasheet, PDF (276/344 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
21.3 Pin Name Conventions
The text that follows describes the SPI. The SPI I/O pin names are SS (slave
select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave
in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel
I/O ports.
The full names of the SPI I/O pins are shown in Table 21-1. The generic pin names
appear in the text that follows.
Table 21-1. Pin Name Conventions
SPI Generic
Pin Names:
Full SPI
Pin Names:
SPI
MISO
PTD1/MISO
MOSI
PTD2/MOSI
SS
PTD0/SS
SPSCK
PTD3/SPSCK
CGND
V_SS
21.4 Functional Description
Figure 21-1 summarizes the SPI I/O registers and Figure 21-2 shows the structure
of the SPI module.
The SPI module allows full-duplex, synchronous, serial communication between
the MCU and peripheral devices, including other MCUs. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
If a port bit is configured for input, then an internal pullup device may be enabled
for that port bit. See 17.4.3 Port C Input Pullup Enable Register.
The following paragraphs describe the operation of the SPI module.
Addr.
Register Name
Read:
$0010
SPI Control Register (SPCR)
See page 293.
Write:
Reset:
SPI Status and Control Reg- ^Read:
$0011
ister (SPSCR) Write:
See page 295. _Reset:
$0012
SPI Data Register ^Read:
(SPDR) Write:
See page 297. _Reset:
Bit 7
SPRIE
0
SPRF
0
R7
T7
R
6
R
0
ERRIE
0
R6
T6
5
SPMSTR
1
OVRF
0
R5
T5
= Reserved
4
3
2
CPOL
CPHA SPWOM
0
MODF
1
SPTE
0
MODFEN
0
1
0
R4
R3
R2
T4
T3
T2
Unaffected by reset
= Unimplemented
1
SPE
0
SPR1
0
R1
T1
Figure 21-1. SPI I/O Register Summary
Bit 0
SPTIE
0
SPR0
0
R0
T0
Data Sheet
276
Serial Peripheral Interface (SPI) Module
MC68HC908GZ8
Freescale Semiconductor