MC68HC908GZ8 Datasheet, PDF (214/344 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Ports
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins
that are being used by the ESCI module. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the states of
the pins. See Table 17-6.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the ESCI module.
When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the
PTE1/RxD pin is available for general-purpose I/O. See Section 19. Enhanced
Serial Communications Interface (ESCI) Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the ESCI module. When the
enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE0/TxD
pin is available for general-purpose I/O. See Section 19. Enhanced Serial
Communications Interface (ESCI) Module.
17.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or
an output. Writing a logic 1 to a DDRE bit enables the output buffer for the
corresponding port E pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
0
0
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1
0
0
0
0
0
0
0
= Unimplemented
Figure 17-18. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
NOTE:
DDRE5–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE5–DDRE0, configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
Avoid glitches on port E pins by writing to the port E data register before changing
data direction register E bits from 0 to 1.
Figure 17-19 shows the port E I/O logic.
Data Sheet
214
Input/Output (I/O) Ports
MC68HC908GZ8
Freescale Semiconductor