MC68HC908GZ8 Datasheet, PDF (302/344 Pages) Motorola, Inc – Microcontrollers

Timebase Module (TBM)
22.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if
the internal clock generator has been enabled to operate during stop mode through
the OSCENINSTOP bit in the configuration register. The timebase module can be
used in this mode to generate a periodic wakeup from stop mode.
If the internal clock generator has not been enabled to operate in stop mode, the
timebase module will not be active during stop mode. In stop mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce power
consumption by disabling the timebase module before executing the STOP
instruction.
22.7 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is
used to enable the timebase interrupts and set the rate.
Address: $001C
Read:
Write:
Reset:
Bit 7
TBIF
0
6
5
TBR2
TBR1
0
0
= Unimplemented
4
TBR0
0
3
0
TACK
0
R
2
1
TBIE
TBON
0
0
= Reserved
Bit 0
R
0
Figure 22-2. Timebase Control Register (TBCR)
NOTE:
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2–TBR0 — Timebase Divider Selection Bits
These read/write bits select the tap in the counter to be used for timebase
interrupts as shown in Table 22-1.
Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK— Timebase Acknowledge Bit
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this
bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no
effect.
1 = Clear timebase interrupt flag
0 = No effect
Data Sheet
302
Timebase Module (TBM)
MC68HC908GZ8
Freescale Semiconductor