MC68HC908GZ8 Datasheet, PDF (318/344 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: ^{Bit 7}
6
5
4
3
2
1
Bit 0
Reset:
1
1
1
1
1
1
1
1
Figure 23-8. TIM Counter Modulo Register Low (TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
23.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture
trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
6
5
Read:
Write:
CH0F
0
CH0IE
MS0B
Reset:
0
0
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Figure 23-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
6
5
Read: CH1F
0
Write:
0
CH1IE
Reset:
0
0
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Figure 23-10. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIM counter registers matches the
value in the TIM channel x registers.
Data Sheet
318
Timer Interface Module (TIM)
MC68HC908GZ8
Freescale Semiconductor