MC68HC908GZ8 Datasheet, PDF (60/344 Pages) Motorola, Inc – Microcontrollers

Resets and Interrupts
4.3.2.12 Scalable Controller Area Network Module (MSCAN)
MSCAN08 interrupt sources:
• MSCAN08 transmitter empty bits (TXE0–TXE2) — The TXEx bit is set when
the corresponding MSCAN08 data buffer is empty. The MSCAN08 transmit
interrupt enable bits, TXEIE0–TXEIE2, enables transmitter CPU interrupt
requests. TXEx is in MSCAN08 transmitter flag register. TXEIEx is in
MSCAN08 transmitter control register.
• MSCAN08 receiver full bit (RXF) — The RXF bit is set when the a MSCAN08
message has been successfully received and loaded into the foreground
receive buffer. The MSCAN08 receive interrupt enable bit, RXFIE, enables
receiver CPU interrupt requests. RXF is in MSCAN08 receiver flag register.
RXFIE is in MSCAN08 receiver interrupt enable register.
• MSCAN08 wakeup bit (WUPIF) — WUPIF is set when activity on the CAN
bus occurred during the MSCAN08 internal sleep mode. The wakeup
interrupt enable bit, WUPIE, enables MSCAN08 wakeup CPU interrupt
requests. WUPIF is in MSCAN08 receiver flag register. WUPIE is in
MSCAN08 receiver interrupt enable register.
• Overrun bit (OVRIF) — OVRIF is set when both the foreground and the
background receive message buffers are filled with correctly received
messages and a further message is being received from the bus. The
overrun interrupt enable bit, OVRIE, enables OVRIF to generate MSCAN08
error CPU interrupt requests. OVRIF is in MSCAN08 receiver flag register.
OVRIE is in MSCAN08 receiver interrupt enable register.
• Receiver Warning bit (RWRNIF) — RWRNIF is set when the receive error
counter has reached the CPU warning limit of 96. The receiver warning
interrupt enable bit, RWRNIE, enables RWRNIF to generate MSCAN08
error CPU interrupt requests. RWRNIF is in MSCAN08 receiver flag register.
RWRNIE is in MSCAN08 receiver interrupt enable register.
• Transmitter Warning bit (TWRNIF) — TWRNIF is set when the transmit error
counter has reached the CPU warning limit of 96. The transmitter warning
interrupt enable bit, TWRNIF, enables TWRNIF to generate MSCAN08 error
CPU interrupt requests. TWRNIF is in MSCAN08 receiver flag register.
TWRNIE is in MSCAN08 receiver interrupt enable register.
• Receiver Error Passive bit (RERRIF) — RERRIF is set when the receive
error counter has exceeded the error passive limit of 127 and the MSCAN08
has gone to error passive state. The receiver error passive interrupt enable
bit, RERRIE, enables RERRIF to generate MSCAN08 error CPU interrupt
requests. RERRIF is in MSCAN08 receiver flag register. RERRIE is in
MSCAN08 receiver interrupt enable register.
• Transmitter Error Passive bit (TERRIF) — TERRIF is set when the transmit
error counter has exceeded the error passive limit of 127 and the MSCAN08
has gone to error passive state. The transmit error passive interrupt enable
bit, TERRIE, enables TERRIF to generate MSCAN08 error CPU interrupt
Data Sheet
60
Resets and Interrupts
MC68HC908GZ8
Freescale Semiconductor