MC68HC908GZ8 Datasheet, PDF (191/344 Pages) Motorola, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
Programmer’s Model of Control Registers
NOTE:
To ensure data integrity, no registers of the receive buffer shall be read while the
RXF flag is cleared.
The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is
set.
16.13.6 MSCAN08 Receiver Interrupt Enable Register
Address:
Read:
Write:
Reset:
$0505
Bit 7
WUPIE
0
6
5
RWRNIE TWRNIE
0
0
4
RERRIE
0
3
TERRIE
0
2
BOFFIE
0
1
OVRIE
0
Figure 16-20. Receiver Interrupt Enable Register (CRIER)
Bit 0
RXFIE
0
NOTE:
WUPIE — Wakeup Interrupt Enable
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
RWRNIE — Receiver Warning Interrupt Enable
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
TWRNIE — Transmitter Warning Interrupt Enable
1 = A transmitter warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
RERRIE — Receiver Error Passive Interrupt Enable
1 = A receiver error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
TERRIE — Transmitter Error Passive Interrupt Enable
1 = A transmitter error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
BOFFIE — Bus-Off Interrupt Enable
1 = A bus-off event will result in an error interrupt.
0 = No interrupt is generated from this event.
OVRIE — Overrun Interrupt Enable
1 = An overrun event will result in an error interrupt.
0 = No interrupt is generated from this event.
RXFIE — Receiver Full Interrupt Enable
1 = A receive buffer full (successful message reception) event will result in a
receive interrupt.
0 = No interrupt will be generated from this event.
The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is
set.
MC68HC908GZ8
Freescale Semiconductor
MSCAN08 Controller (MSCAN08)
Data Sheet
191