MC68HC908GZ8 Datasheet, PDF (263/344 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Exception Control
20.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
20.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the
stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end
of an interrupt, the RTI instruction recovers the CPU register contents from the
stack so that normal processing can resume. Figure 20-8 shows interrupt entry
timing. Figure 20-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE
INTERRUPT
Figure 20-8. Interrupt Entry Timing
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
R/W
Figure 20-9. Interrupt Recovery Timing
MC68HC908GZ8
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
263