MC68HC908GZ8 Datasheet, PDF (146/344 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
until either V_DD goes above the rising 5-V trip point, V_TRIPR, which will release reset
or V_DD decreases to approximately 0 V which will re-trigger the power-on reset and
reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register
(CONFIG1). See Figure 8-2. Configuration Register 1 (CONFIG1) for details of
the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V_DD rises above a voltage, V_TRIPR, which causes the MCU to exit reset. See
20.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the
SIM and the LVI. The output of the comparator controls the state of the LVIOUT
flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to
external peripheral devices.
V_DD
LVIPWRD
FROM CONFIG
STOP INSTRUCTION
FROM CONFIG1
LVIRSTD
LVISTOP
FROM CONFIG1
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVI5OR3
FROM CONFIG1
LVIOUT
LVI RESET
Figure 14-1. LVI Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
$FE0C
LVI Status Register (LVISR)
See page 147.
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
Data Sheet
146
Low-Voltage Inhibit (LVI)
MC68HC908GZ8
Freescale Semiconductor