MC68HC711D3CFNE2 Datasheet, PDF (99/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
RTR[1:0]
00
01
10
11
E = 1 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
E = 2 MHz
4.096 ms
8.192 ms
16.384 ms
32.768 ms
E = 3 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
E = X MHz
(E/2¹³)
(E/2¹⁴)
(E/2¹⁵)
(E/2¹⁶)
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire real-time interrupt period elapses before
the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL regis-
ters.
9.4.1 Timer Interrupt Mask 2 Register
This register contains the real-time interrupt enable bits.
TMSK2 — Timer Interrupt Mask 2
Bit 7
6
5
4
3
TOI
RTII
PAOVI
PAII
0
RESET:
0
0
0
0
0
TOI — Timer Overflow Interrupt Enable
Refer to 9.3 Output Compare.
$0024
2
1
Bit 0
0
PR1
PR0
0
0
0
RTII — Real-time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one
PAOVI — Pulse Accumulator Overflow Interrupt Enable
Refer to 9.6 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge
Refer to 9.6 Pulse Accumulator.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
9.4.1 Timer Interrupt Flag 2 Register
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
TECHNICAL DATA
TIMING SYSTEM
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9-13