MC68HC711D3CFNE2 Datasheet, PDF (57/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
2A
Y
BIT I IN
CCR = 1?
N
ANY I-BIT _Y
INTERRUPT
PENDING?
N
FETCH OPCODE
STACK CPU
REGISTERS
STACK CPU
REGISTERS
SET BIT I IN CCR
FETCH VECTOR
$FFF8, $FFF9
Y
ILLEGAL
OPCODE?
N
WAI
Y
INSTRUCTION?
N
STACK CPU
REGISTERS
SET BIT I IN CCR
Y
SWI
INSTRUCTION?
N
FETCH VECTOR
$FFF6, $FFF7
Y
RTI
INSTRUCTION?
RESTORE CPU
REGISTERS
FROM STACK
N
EXECUTE THIS
INSTRUCTION
STACK CPU
REGISTERS
N
ANY
INTERRUPT
PENDING?
Y
SET BIT I IN CCR
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE FIGURE 5–2
1A
FLOW OUT OF RESET P2
Figure 5-1 Processing Flow out of Reset (2 of 2)
TECHNICAL DATA
RESETS AND INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
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