MC68HC711D3CFNE2 Datasheet, PDF (46/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
COP is enabled, the software is responsible for keeping a free-running watchdog timer
from timing out. When the software is no longer being executed in the intended se-
quence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP sys-
tem is enabled or disabled. In normal modes, COP is enabled out of reset and does
not depend on software action. To disable the COP system, set the NOCOP bit in the
CONFIG register. In the special test and bootstrap operating modes, the COP system
is initially inhibited by the disable resets (DISR) control bit in the TEST1 register. The
DISR bit can subsequently be written to zero to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
time-out period. The system E clock is divided by 2¹⁵ and then further scaled by a fac-
tor shown in Table 5-1. After reset, these bits are zero, which selects the fastest time-
out period. In normal operating modes, these bits can only be written once within 64
bus cycles after reset.
CR[1:0]
00
01
10
11
Divide
E/2¹⁵
By
1
4
16
64
E=
Table 5-1 COP Time-out
XTAL = 4.0 MHz
Time-out
–0/+32.8 ms
32.768 ms
131.072 ms
524.288 ms
2.097 sec
1.0 MHz
XTAL = 8.0 MHz
Time-out
–0/+16.4 ms
16.384 ms
65.536 ms
262.140 ms
1.049 sec
2.0 MHz
XTAL = 12.0 MHz
Time-out
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
COPRST — Am/Reset COP Timer Circuitry
$003A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
Complete the following reset sequence to service the COP timer. Write $55 to CO-
PRST to arm the COP timer clearing mechanism. Then write $AA to COPRST to clear
the COP timer. Performing instructions between these two steps is possible as long as
both steps are completed in the correct sequence before the timer times out.
5.1.4 Clock Monitor Reset
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges
are detected within this RC time delay, the clock monitor can optionally generate a sys-
tem reset. The clock monitor function is enabled or disabled by the CME control bit in
the OPTION register. The presence of a time-out is determined by the RC delay, which
allows the clock monitor to operate without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a
clock to function, it is disabled when the clocks stop. Therefore, the clock monitor sys-
tem can detect clock failures not detected by the COP system.
RESETS AND INTERRUPTS
5-2
TECHNICAL DATA
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