MC68HC711D3CFNE2 Datasheet, PDF (96/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
TCTL1 — Timer Control 1
$0020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0
0
0
0
0
0
0
0
OM[2:5] — Output Mode
OL[2:5] — Output Level
These control bit pairs are encoded to specify the action taken after a successful OCx
compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to
the following table for the coding.
OMx
0
0
1
1
OLx
Action Taken on Successful Compare
0
Timer disconnected from output pin logic
1
Toggle OCx output line
0
Clear OCx output line to 0
1
Set OCx output line to 1
9.3.7 Timer Interrupt Mask 1 Register
Use this 8-bit register to enable or inhibit the timer input capture and output compare
interrupts.
TMSK1 — Timer Interrupt Mask 1
Bit 7
6
5
4
3
2
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
RESET:
0
0
0
0
0
0
$0022
1
Bit 0
IC2I
IC3I
0
0
OC1I–OC4I — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-
quence is requested.
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When
I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence
is requested.
NOTE
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
9.3.8 Timer Interrupt Flag 1 Register
Bits in this register indicate when timer system events have occurred. Coupled with the
bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a
9-10
TIMING SYSTEM
For More Information On This Product,
Go to: www.freescale.com
TECHNICAL DATA