MC68HC711D3CFNE2 Datasheet, PDF (113/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table A-6 Expansion Bus Timing
Num
Characteristic
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min Max
Frequency of Operation (E-Clock
Frequency)
f_o
dc
1.0
dc
2.0
dc
3.0 MHz
1 Cycle Time
t_cyc
1000
—
500
—
333
— ns
2 Pulse Width, E Low
PW_EL = 1/2 t_cyc - 23ns
PW_EL
477
—
227
—
146
— ns
3 Pulse Width, E High
PW_EH = 1/2 t_cyc - 28 ns
PW_EH
472
—
222
—
141
— ns
4A E and AS Rise Time
4B E and AS Fall Time
t_r
—
20
—
20
—
20 ns
t_f
—
20
—
20
—
15 ns
9 Address Hold Time
t_AH = 1/8 t_cyc - 29.5 ns
t_AH
95.5
—
33
—
26
— ns
(Note 1a)
12 Non-Muxed Address Valid Time to E Rise t_AV
281.5
—
94
—
54
— ns
t_AV = PW_EL - (t_ASD + 80 ns) (Note 1a)
17 Read Data Setup Time
t_DSR
30
—
30
—
30
— ns
18 Read Data Hold Time (Max = t_MAD)
t_DHR
0
145.5
0
83
0
51 ns
19 Write Data Delay Time
t_DDW = 1/8 t_cyc + 65.5 ns
t_DDW
(Note 1a)
—
190.5
—
128
—
71 ns
21 Write Data Hold Time
t_DHW = 1/8 t_cyc - 30 ns
t_DHW
95.5
—
33
—
26
— ns
(Note 1a)
22 Muxed Address Valid Time to E Rise
t_AVM
271.5
—
84
—
54
— ns
t_AVM = PW_{EL -} (t_ASD + 90 ns) (Note 1a)
24 Muxed Address Valid Time to AS Fall
t_ASL = PW_ASH - 70 ns
t_ASL
151
—
26
—
13
— ns
25 Muxed Address Hold Time
t_AHL
95.5
—
33
—
31
— ns
t_AHL = 1/8 t_cyc - 30 ns
(Note 1b)
26 Delay Time, E to AS Rise
t_ASD
115.5
—
53
—
31
— ns
t_ASD = 1/8 t_cyc - 5 ns
(Note 1a)
27 Pulse Width, AS High
PW_ASH = 1/4 t_cyc - 30 ns
PW_ASH
221
—
96
—
63
— ns
28 Delay Time, AS to E Rise
t_ASED
115.5
—
53
—
31
— ns
t_ASED = 1/8 t_cyc - 5 ns
(Note 1b)
29 MPU Address Access Time (Note 1a) t_ACCA 744.5
—
307
—
196
— ns
t_ACCA = t_cyc – (PW_EL– t_AVM) – t_DSR–t_f
35 MPU Access Time
t_ACCE = PW_EH - t_DSR
t_ACCE
—
442
—
192
—
111 ns
36 Muxed Address Delay
(Previous Cycle MPU Read)
t_MAD
145.5
—
83
—
51
— ns
t_MAD = t_ASD + 30 ns(Note 1a)
NOTES:
1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock
duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following
expressions in place of 1/8 t_cyc in the above formulas, where applicable:
(a) (1-DC) × 1/4 t_cyc
(b) DC × 1/4 t_cyc
Where:
DC is the decimal value of duty cycle percentage (high time).
2. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
TECHNICAL DATA
A-9
For More Information On This Product,
Go to: www.freescale.com