MC68HC711D3CFNE2 Datasheet, PDF (101/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
RTR[1:0] — RTI Interrupt Rate Select
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 2¹³ rate clock that is compensated so it is in-
dependent of the timer prescaler. These two control bits select an additional division
factor.
RTR[1:0]
00
01
10
11
E = 1 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
E = 2 MHz
4.096 ms
8.192 ms
16.384 ms
32.768 ms
E = 3 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
E = X MHz
(E/2¹³)
(E/2¹⁴)
(E/2¹⁵)
(E/2¹⁶)
9.5 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed dis-
cussion of the COP function.
9.6 Pulse Accumulator
The MC68HC11D3 has an 8-bit counter that can be configured to operate either as a
simple event counter, or for gated time accumulation, depending on the state of the
PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Fig-
ure 9-3.
In the event counting mode, the 8-bit counter is clocked to increasing values by an ex-
ternal pin. The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock ÷ 64
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to
Table 9-3. The pulse accumulator counter can be read or written at any time.
TECHNICAL DATA
TIMING SYSTEM
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