MC68HC711D3CFNE2 Datasheet, PDF (41/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7
6
5
4
3
RBOOT SMOD
MDA
IRVNE
PSEL3
RESET:
—
—
—
—
0
2
PSEL2
1
1
PSEL1
0
$003C
Bit 0
PSEL0
1
The values of the RBOOT, SMOD, IRVNE, and MDA at reset depend on the mode dur-
ing initialization. Refer to Table 4-2.
RBOOT — Read Bootstrap ROM
Has meaning only when the SMOD bit is a one (special bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and located in map at $BF40–$BFFF
SMOD — Special Mode Select
This bit reflects the inverse of the MODB input pin at the rising edge of reset. It is set
if the MODB input pin is low during reset. If MODB is high during reset, it is cleared.
SMOD can be cleared under software control from the special modes, thus changing
the operating mode of the MCU. SMOD can never be set by software.
0 = Normal mode variation in effect
1 = Special mode variation in effect
MDA — Mode Select A
The mode select A bit reflects the status of the MODA input pin at the rising edge of
reset. While the SMOD bit is set (special bootstrap or special test mode in effect), the
MDA bit can be written, thus changing the operating mode of the MCU. When the
SMOD bit is clear, the MODA bit is read-only and the operating mode cannot be
changed without going through a reset sequence.
0 = Normal single-chip or special bootstrap mode in effect
1 = Normal expanded or special test mode in effect
IRVNE — Internal Read Visibility/Not E
The IRVNE control bit allows internal read accesses to be available on the external
data bus during factory testing or emulation. If this capability is used for other purpos-
es, bus conflicts can occur because the bidirectional data bus is driven out during a
read of internal addresses, even though the R/W line suggests a high impedance
read mode.
0 = No internal read visibility on external bus
1 = Internal read data driven out data bus
In single-chip modes, this bit determines whether the E clock drives out of the chip.
0 = E driven out
1 = E pin driven low
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
4-7
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