MC68HC711D3CFNE2 Datasheet, PDF (29/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table 3-2 Instruction Set (Sheet 2 of 7)
Mnemonic Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode Operand Cycles S X H I N Z V C
BCLR (opr)
Clear Bit(s)
(msk)
M • (mm) ⇒ M
DIR
IND,X
IND,Y 18
15 dd mm
1D ff mm
1D ff mm
6
———— ∆ ∆ 0 —
7
8
BCS (rel) Branch if Carry
Set
?C=1
REL
25 rr
3
————————
BEQ (rel)
Branch if =
Zero
?Z=1
REL
27 rr
3
————————
BGE (rel)
Branch if ∆
?N⊕V=0
REL
2C rr
3
————————
Zero
BGT (rel)
Branch if > ? Z + (N ⊕ V) = 0
REL
Zero
2E rr
3
————————
BHI (rel)
Branch if
Higher
?C+Z=0
REL
22 rr
3
————————
BHS (rel)
Branch if
Higher or
Same
?C=0
REL
24 rr
3
————————
BITA (opr)
Bit(s) Test A
with Memory
A•M
A
IMM
85 ii
A
DIR
95 dd
A
EXT
B5 hh ll
A
IND,X
A5 ff
A
IND,Y 18
A5 ff
2 ^{———— ∆ ∆ 0 —}
3
4
4
5
BITB (opr)
Bit(s) Test B
with Memory
B•M
B
IMM
C5 ii
B
DIR
D5 dd
B
EXT
F5 hh ll
B
IND,X
E5 ff
B
IND,Y 18
E5 ff
2 ^{———— ∆ ∆ 0 —}
3
4
4
5
BLE (rel)
Branch if ∆ ? Z + (N ⊕ V) = 1
REL
Zero
2F rr
3 ^{————————}
BLO (rel)
Branch if
Lower
?C=1
REL
25 rr
3 ^{————————}
BLS (rel)
Branch if
?C+Z=1
REL
23 rr
3 ^{————————}
Lower or
Same
BLT (rel)
Branch if <
?N⊕V=1
REL
2D rr
3 ^{————————}
Zero
BMI (rel)
Branch if
Minus
?N=1
REL
2B rr
3 ^{————————}
BNE (rel) Branch if not =
Zero
?Z=0
REL
26 rr
3 ^{————————}
BPL (rel) Branch if Plus
?N=0
REL
2A rr
3 ^{————————}
BRA (rel) Branch Always
?1=1
REL
20 rr
3 ^{————————}
BRCLR(opr)
(msk)
(rel)
Branch if
Bit(s) Clear
? M • mm = 0
DIR
IND,X
IND,Y 18
13 dd mm rr ₆
1F ff mm rr
7
1F ff mm rr
8
————————
BRN (rel) ^{Branch Never}
?1=0
REL
21 rr
3 ^{————————}
BRSET(opr) Branch if Bit(s) _{? (M) • mm = 0}
(msk)
Set
(rel)
DIR
IND,X
IND,Y 18
12 dd mm rr ₆
1E ff mm rr
7
1E ff mm rr
8
————————
BSET (opr)
Set Bit(s)
(msk)
M + mm ⇒ M
DIR
IND,X
IND,Y 18
14 dd mm
1C ff mm
1C ff mm
6 ^{———— ∆ ∆ 0 —}
7
8
BSR (rel) ^{Branch to} See Figure 3–2
REL
Subroutine
8D rr
6 ^{————————}
BVC (rel) ^{Branch if}
Overflow Clear
?V=0
REL
28 rr
3 ^{————————}
BVS (rel) ^{Branch if}
Overflow Set
?V=1
REL
29 rr
3 ^{————————}
CBA
CLC
Compare A to
B
Clear Carry Bit
A–B
0⇒C
INH
11
—
2 ^{———— ∆ ∆ ∆ ∆}
INH
0C
—
2 ^{——————— 0}
CLI
Clear Interrupt
Mask
0⇒I
INH
0E
—
2 ^{——— 0 ————}
CLR (opr) ^{Clear Memory}
Byte
0⇒M
EXT
IND,X
IND,Y 18
7F hh ll
6F ff
6F ff
6 ^{———— 0 1 0 0}
6
7
CENTRAL PROCESSING UNIT
TECHNICAL DATA
3-9
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