MC68HC711D3CFNE2 Datasheet, PDF (21/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
SECTION 3
CENTRAL PROCESSING UNIT
This section presents information on M68HC11 central processing unit (CPU) archi-
tecture, data types, addressing modes, the instruction set, and special operations,
such as subroutine calls and interrupts.
The CPU is designed to treat all peripheral, I/O, and memory locations identically as
addresses in the 64 Kbyte memory map. This is referred to as memory-mapped I/O.
There are no special instructions for I/O that are separate from those used for memory.
This architecture also allows accessing an operand from an external memory location
with no execution-time penalty.
3.1 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if
they were memory locations. The seven registers, discussed in the following para-
graphs, are shown in Figure 3-1.
7
A
07
B
0 8-BIT ACCUMULATORS A & B
15
D
0 OR 16-BIT DOUBLE ACCUMULATOR D
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PC
7
0
SXH I NZVC
PROGRAM COUNTER
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
HC11 PROG MODEL
Figure 3-1 Programming Model
CENTRAL PROCESSING UNIT
TECHNICAL DATA
3-1
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