MC68HC711D3CFNE2 Datasheet, PDF (63/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
SECTION 6
PARALLEL I/O
The MC68HC11D3 has four 8-bit I/O ports; A, B, C, and D. In single-chip and bootstrap
modes, all ports are parallel I/O data ports. In expanded multiplexed and test modes,
ports B and C, and lines DATA6/AS and DATA7/R/W are a memory expansion bus
with port B as the high order address bus, port C as the multiplexed address and data
bus, AS as the demultiplexing signal, and R/W as the data bus direction control. Refer
to Table 6-1, which is a summary of the ports and their shared functions:
Port
Port A
Port B
Port C
Port D
Table 6-1 I/O Ports
Input Pins
3
—
—
—
Output Pins
3
—
—
—
Bidirectional Pins
2
8
8
8
Shared Functions
TImer
High Order Address
Low Order Address and Data Bus
SCI, SPI, AS, and R/
6.1 Port A
Port A bits handle the timer functions and can also be used as general-purpose I/O. In
both the normal operating modes, port A can be configured for four timer input capture
(IC) and three timer output compare (OC) functions, or four OC and three IC functions
with either a pulse accumulator input (PAI) or a fifth OC function.
PORTA — Port A Data
Bit 7
6
5
4
3
2
PA7
PA6*
PA5
PA4*
PA3
PA2
RESET:
HiZ
0
0
0
HiZ
HiZ
Alt. Func:
And/or:
PAI
OC1
OC2
OC1
OC3
OC1
OC4
IC4/OC5
IC1
OC1
OC1
—
*This pin is not bonded in the 40-pin version.
$0000
1
Bit 0
PA1
PA0
HiZ
HiZ
IC2
IC3
—
—
6.2 Port B
In single-chip mode, all port B pins are general-purpose I/O (PB[7:0]). In expanded
multiplexed mode, all port B pins act as high-order address bits (ADDR[15:8]).
PORTB — Port B Data
S. Chip
or Boot:
RESET:
Expan.
or Test:
RESET:
Bit 7
PB7
PB7
ADDR15
6
5
4
3
2
1
PB6
PB5
PB4
PB3
PB2
PB1
PB6
PB5
PB4
PB3
PB2
PB1
Reset configures pins as HiZ inputs
ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9
Reset configures pins as high-order address outputs
$0004
Bit 0
PB0
PB0
ADDR8
PARALLEL I/O
TECHNICAL DATA
6-1
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