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MC68HC711D3CFNE2 Datasheet, PDF (73/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes
Freescale Semiconductor, Inc.
SBK — Send Break
At least one character time of break is queued and sent each time SBK is written to
one. More than one break may be sent if the transmitter is idle at the time the SBK bit
is toggled on and off, as the baud rate clock edge could occur between writing the one
and writing the zero to SBK.
0 = Break generator off
1 = Break codes generated as long as SBK = 1
7.6.4 Serial Communication Status Register (SCSR)
The SCSR provides inputs to the interrupt logic circuits for generation of the SCI sys-
tem interrupt.
SCSR — SCI Status Register
$002E
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
RESET:
1
1
0
0
0
0
0
0
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with
TDRE set and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission
in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF
flag by reading SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD
line has been active and becomes idle again. The IDLE flag is inhibited when RWU =
1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR — Overrun Error Flag
OR is set if a new character is received before a previously received character is read
from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR.
0 = No overrun
1 = Overrun detected
SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
7-7
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