MC68HC711D3CFNE2 Datasheet, PDF (44/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
4.2.2.3 OPTION Register
The 8-bit special-purpose OPTION register sets internal system configuration options
during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be
written to only once after a reset and then they become read-only. This minimizes the
possibility of any accidental changes to the system configuration.
OPTION — System Configuration Options
$0039
Bit 7
6
5
4
3
2
1
Bit 0
0
0
IRQE*
DLY*
CME
0
CR1*
CR0*
RESET:
0
0
0
1
0
0
0
0
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
Bits [7:6] and 2 — Not implemented
Always read zero
IRQE — IRQ Select Edge Sensitive only
0 = IRQ is configured for level sensitive operation
1 = IRQ is configured for edge sensitive only operation
DLY — Enable Oscillator Startup Delay
0 = The oscillator startup delay coming out of STOP is bypassed and the MCU re-
sumes processing within about four bus cycles.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
up from the STOP power-saving mode. This delay allows the crystal oscillator
to stabilize.
CME — Clock Monitor Enable
Refer to SECTION 5 RESETS AND INTERRUPTS.
CR[1:0] — COP Timer Rate Select Bits
The internal E clock is first divided by 2¹⁵ before it enters the COP watchdog system.
These control bits determine a scaling factor for the watchdog timer. Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
4-10
OPERATING MODES AND ON-CHIP MEMORY
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TECHNICAL DATA