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MC68HC711D3CFNE2 Datasheet, PDF (115/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes
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Freescale Semiconductor, Inc.
Table A-7 Serial Peripheral Interface Timing
Num
Characteristic
Symbol
2.0 MHz
Min Max
Operating Frequency
Master
Slave
1 Cycle Time
Master
Slave
2 Enable Lead Time
Master (Note 2)
Slave
3 Enable Lag Time
Master (Note 2)
Slave
4 Clock (SCK) High Time
Master
Slave
5 Clock (SCK) Low Time
Master
Slave
6 Data Setup Time (Inputs)
Master
Slave
7 Data Hold Time (Inputs)
Master
Slave
8 Access Time
(Time to Data Active from High-Imp. State)
Slave
9 Disable Time
(Hold Time to High-Impedance State)
Slave
10 Data Valid (After Enable Edge) (Note 3)
11 Data Hold Time (Outputs) (After Enable Edge)
12 Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
13 Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
fop(m)
fop(s)
dc
0.5
dc
2.0
tcyc(m)
tcyc(s)
2.0
—
500
—
tlead(m)
—
—
tlead(s)
250
—
tlag(m)
tlag(s)
—
—
250
—
tw(SCKH)m 340
—
tw(SCKH)s
190
—
tw(SCKL)m
340
—
tw(SCKL)s
190
—
tsu(m)
tsu(s)
100
—
100
—
th(m)
th(s)
100
—
100
—
ta
0
120
tdis
—
240
tv(s)
—
240
tho
0
—
trm
—
100
trs
—
2.0
tfm
—
100
tfs
—
2.0
NOTES:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 100 pF load on all SPI pins.
3.0 MHz
Min Max
dc
0.5
dc
3.0
2.0
—
333
—
—
—
240
—
—
—
240
—
340
—
190
—
340
—
190
—
100
—
100
—
100
—
100
—
0
120
—
167
—
167
0
—
—
100
—
2.0
—
100
—
2.0
Unit
fop
MHz
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
TECHNICAL DATA
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-11
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