MC68HC711D3CFNE2 Datasheet, PDF (97/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in
the same position.
TFLG1 — Timer Interrupt Flag 1
RESET:
Bit 7
OC1F
0
6
OC2F
0
5
OC3F
0
4
OC4F
0
3
I4/O5F
0
2
IC1F
0
Clear flags by writing a one to the corresponding bit position(s).
1
IC2F
0
$0023
Bit 0
IC3F
0
OC1F–OC5F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
9.3.9 Timer Interrupt Mask 2 Register
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The
timer prescaler control bits are included in this register.
TMSK2 — Timer Interrupt Mask 2
Bit 7
6
5
4
3
TOI
RTII
PAOVI
PAII
0
RESET:
0
0
0
0
0
TOI — Timer Overflow Interrupt Enable
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to one
$0024
2
1
Bit 0
0
PR1
PR0
0
0
0
RTII — Real-time Interrupt Enable
Refer to 9.4 Real-Time Interrupt.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
Refer to 9.6 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge Interrupt Enable
Refer to 9.6 Pulse Accumulator.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
TECHNICAL DATA
TIMING SYSTEM
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