MC68HC711D3CFNE2 Datasheet, PDF (116/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
SS is held high on master.
1
SEE
NOTE
4
5
SEE
NOTE
6
7
12
5
13
4
MISO
(INPUT)
10 (ref)
MSB IN
BIT 6 - - - -1
11
10
MOSI
(OUTPUT)
MASTER MSB OUT
BIT 6 - - - -1
13
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.
13
12
LSB IN
11 (ref)
MASTER LSB OUT
12
SPI MASTER CPHA0 TIM
Figure A-9 SPI Master Timing (CPHA = 0)
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
10 (ref)
SS is held high on master.
1
12
5
4
5
4
MSB IN
MASTER MSB OUT
13
12
BIT 6 - - - -1
11
10
BIT 6 - - - -1
NOTE: This last clock edge is generated internally but is not seen at the SCK pin.
13
13
6
7
LSB IN
SEE
NOTE
SEE
NOTE
11 (ref)
MASTER LSB OUT
12
SPI MASTER CPHA1 TIM
Figure A-10 SPI Master Timing (CPHA = 1)
A-12
ELECTRICAL CHARACTERISTICS
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TECHNICAL DATA