MC68HC711D3CFNE2 Datasheet, PDF (42/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Mode
Single-Chip
Expanded
Boot
Special Test
IRVNE Out
of Reset
0
0
0
1
E Clock Out
of Reset
On
On
On
On
IRV Out of
Reset
Off
Off
Off
On
IRVNE
Affects Only
E
IRV
E
IRV
PSEL[3:0] — Priority Select Bits
Refer to SECTION 5 RESETS AND INTERRUPTS.
4.2.2 System Initialization
Registers and bits that control initialization and the basic configuration of the MCU are
protected against writes except under special circumstances. The protection mecha-
nism, overridden in special operating modes, permits writing these bits only within the
first 64 bus cycles after any reset, and then only once after each reset. If the MCU is
going to be changed to a normal mode after being reset in a special mode, write to the
protected registers before writing the SMOD control bit to zero.
4.2.2.1 CONFIG Register
The CONFIG register consists of static latches that control the startup configuration of
the MCU. CONFIG is writable only once in expanded and single-chip modes (SMOD
= 0). In these modes, the COP watchdog timer is enabled out of reset.
CONFIG — System Configuration
$003F
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
NOCOP ROMON
0
RESET:
0
0
0
0
0
—
—
0
Bits [7:3] and 0 — Not implemented
Always read zero
NOCOP — COP System Disable
This bit is cleared out of reset in normal modes (COP enabled). Refer to SECTION 5
RESETS AND INTERRUPTS.
0 = COP system enabled
1 = COP system disabled
ROMON — ROM Enable
In all modes, ROMON is forced to one out of reset. Writable once in normal modes and
writable at any time in special modes.
0 = ROM removed from the memory map
1 = ROM present in the memory map
OPERATING MODES AND ON-CHIP MEMORY
4-8
TECHNICAL DATA
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