MC68HC711D3CFNE2 Datasheet, PDF (81/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
SCK CYCLE #
SCK (CPOL = 0)
1
2
3
4
5
6
7
8
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
SAMPLE INPUT
(CPHA = 1) DATA OUT
SS (TO SLAVE)
MSB
6
MSB
3
2
1
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
5
4
3
2
1
6
5
4
3
2
SLAVE CPHA=1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA=0 TRANSFER IN PROGRESS
LSB
1
LSB
4
5
SPI TRANSFER FORMAT 1
Figure 8-2 SPI Transfer Format
8.2.1 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using
two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL
control bit, which selects an active high or active low clock, and has no significant ef-
fect on the transfer format. The clock phase (CPHA) control bit selects one of two dif-
ferent transfer formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the phase and polar-
ity are changed between transfers to allow a master device to communicate with pe-
ripheral slaves having different requirements.
When CPHA equals zero, the slave select (SS) line must be negated and reasserted
between each successive serial byte. Also, if the slave writes data to the SPI data reg-
ister (SPDR) while SS is active low, a write collision error results.
When CPHA equals one, the SS line can remain low between successive transfers.
8.3 SPI Signals
The following paragraphs contain descriptions of the four SPI signals: master in slave
out (MISO), master out slave in (MOSI), serial clock (SCK), and SS.
SERIAL PERIPHERAL INTERFACE
TECHNICAL DATA
8-3
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