MC68HC711D3CFNE2 Datasheet, PDF (95/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
OC1M — Output Compare 1 Mask
Bit 7
6
5
4
3
2
1
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
0
0
RESET:
0
0
0
0
0
0
0
OC1M7–OC1M3 — Output Compare Masks
0 = OC1 is disabled
1 = OC1 is enabled to control the corresponding pin of port A
Bits [2:0] — Not implemented; always read zero
Set bit(s) to enable OC1 to control corresponding pin(s) of port A.
$000C
Bit 0
0
0
9.3.4 Output Compare 1 Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin
of port A after a successful OC1 compare. When a successful OC1 compare occurs,
a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in
OC1M.
OC1D — Output Compare 1 Data
$000D
Bit 7
6
5
4
3
2
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
0
RESET:
0
0
0
0
0
0
1
Bit 0
0
0
0
0
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] — Not implemented; always read zero
9.3.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A
full counter read addresses the most significant byte (MSB) first. A read of this address
causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-
cle so that a double-byte read returns the full 16-bit state of the counter at the time of
the MSB read cycle.
TCNT — Timer Counter
$000E, $000F
$000E
Bit 15
14
13
12
11
10
9
Bit 8
$000F
Bit 7
6
5
4
3
2
1
Bit 0
TCNT (High)
TCNT (Low)
TCNT resets to $0000.
In normal modes, TCNT is read-only.
9.3.6 Timer Control 1 Register
The bits of this register specify the action taken as a result of a successful OCx com-
pare.
TIMING SYSTEM
TECHNICAL DATA
9-9
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