MC68HC711D3CFNE2 Datasheet, PDF (22/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

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3.1.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold operands and re-
sults of arithmetic calculations or data manipulations. For some instructions, these two
accumulators are treated as a single double-byte (16-bit) accumulator called accumu-
lator D. Although most operations can use accumulators A or B interchangeably, the
following exceptions apply:
The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents
of 16-bit register X or Y, but there are no equivalent instructions that use A instead of B.
The TAP and TPA instructions transfer data from accumulator A to the condition code
register, or from the condition code register to accumulator A, however there are no
equivalent instructions that use B rather than A.
The decimal adjust accumulator (DAA) instruction is used after binary-coded decimal
(BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust ac-
cumulator B.
The add, subtract, and compare instructions associated with both A and B (ABA, SBA,
and CBA) only operate in one direction, making it important to plan ahead to ensure
the correct operand is in the correct accumulator.
3.1.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset
provided in an instruction to create an effective address. The IX register can also be
used as a counter or as a temporary storage register.
3.1.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that of the IX reg-
ister. However, most instructions using the IY register require an extra byte of machine
code and an extra cycle of execution time because of the way the opcode map is im-
plemented. Refer to 3.3 Opcodes and Operands for further information.
3.1.4 Stack Pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be located any-
where in the address space and can be any size up to the amount of memory available
in the system. Normally the SP is initialized by one of the first instructions in an appli-
cation program. The stack is configured as a data structure that grows downward from
high memory to low memory. Each time a new byte is pushed onto the stack, the SP
is decremented. Each time a byte is pulled from the stack, the SP is incremented. At
any given time, the SP holds the 16-bit address of the next free location in the stack.
Figure 3-2 is a summary of SP operations.
CENTRAL PROCESSING UNIT
3-2
TECHNICAL DATA
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