MC68HC711D3CFNE2 Datasheet, PDF (39/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table 4-1 Register and Control Bit Assignments (Continued)
Bit 7
6
5
4
3
2
1
Bit 0
$002B TCLR
0
SCP1 SCP0 RCKB SCR2 SCR1 SCR0
BAUD
$002C
R8
T8
0
M
WAKE
0
0
0
SCCR1
$002D
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCCR2
$002E TDRE
TC
RDRF
IDLE
OR
NF
FE
0
SCSR
$002F R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
SCDR
$0030
Reserved
to
$0038
Reserved
$0039
0
0
IRQE
DLY
CME
0
CR1
CR0
OPTION
$003A
Bit 7
6
5
4
3
2
1
Bit 0 COPRST
$003B
Reserved
$003C RBOOT SMOD MDA IRVNE PSEL3 PSEL2 PSEL1 PSEL0 HPRIO
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
INIT
$003E TILOP
0
OCCR CBYP DISR
FCM
FCOP
0
TEST1
$003F
0
0
0
0
0
NOCOP ROMON
0
CONFIG
The bootloader program is contained in the 192-byte bootstrap ROM. This ROM,
which appears as internal memory space at locations $BF40–$BFFF, is enabled only
if the MCU is reset in special bootstrap mode.
Memory locations are the same for expanded multiplexed and single-chip modes, ex-
cept for ROM in expanded mode and the bootloader ROM in special bootstrap mode.
The on-board 192-byte RAM is initially located at $0040 after reset, but can be placed
at any other 4K boundary ($x040) by writing an appropriate value to the INIT register.
The 4 Kbyte ROM is located at $F000 through $FFFF in all modes except expanded
multiplexed, in which it is located at $7000. ROM can be located at $F000 in expanded
multiplexed by entering single-chip mode out of reset and setting the MDA bit in the
HPRIO register to 1, thereby entering expanded mode from internal ROM. Disable
ROM by clearing the ROMON bit in the CONFIG register.
Hardware priority is built into RAM and I/O remapping. Registers and RAM have prior-
ity over ROM. In the event of conflicts, the higher priority resource takes precedence.
The 192 bytes of fully static RAM store instructions, variables, and temporary data.
The direct addressing mode can access RAM locations using a one-byte address op-
erand, saving program memory space and execution time, depending on the applica-
tion. RAM contents are preserved during periods of processor inactivity by two
methods, both of which reduce power consumption.
In the software-based STOP mode, the clocks are stopped while V_DD powers the
MCU. Because power supply current is directly related to operating frequency in
CMOS integrated circuits, only a very small amount of leakage exists when the clocks
are stopped.
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
4-5
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