MC68HC711D3CFNE2 Datasheet, PDF (43/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
NOTE
In expanded mode, ROM is located at $7000–$7FFF out of reset. In
all other modes, ROM is located at $F000–$FFFF.
4.2.2.2 INIT Register
The internal registers used to control the operation of the MCU can be relocated on 4K
boundaries within the memory space with the use of INIT. This 8-bit special-purpose
register can change the default locations of the RAM and control registers within the
MCU memory map. It can be written to only once within the first 64 E-clock cycles after
a reset, and then it becomes a read-only register.
INIT — RAM and I/O Mapping Register
Bit 7
6
5
RAM3
RAM2
RAM1
RESET:
0
0
0
4
RAM0
0
3
REG3
0
2
REG2
0
1
REG1
0
$003D
Bit 0
REG0
1
RAM[3:0] — RAM Map Position
These four bits, which specify the upper hexadecimal digit of the RAM address, control
position of RAM in the memory map. RAM can be positioned at the beginning of any
4K page in the memory map. It is initialized to address $0040 out of reset. Refer to
Table 4-3.
REG[3:0] — 64-Byte Register Block Position
These four bits specify the upper hexadecimal digit of the address for the 64-byte block
of internal registers. The register block, positioned at the beginning of any 4K page in
the memory map, is initialized to address $0000 out of reset. Refer to Table 4-4.
Table 4-3 RAM Mapping
RAM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address
$0040–$00FF
$1040–$10FF
$2040–$20FF
$3040–$30FF
$4040–$40FF
$5040–$50FF
$6040–$60FF
$7040–$70FF
$8040–$80FF
$9040–$90FF
$A040–$A0FF
$B040–$B0FF
$C040–$C0FF
$D040–$D0FF
$E040–$E0FF
$F040–$F0FF
Table 4-4 Register Mapping
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address
$0000–$003F
$1000–$103F
$2000–$203F
$3000–$303F
$4000–$403F
$5000–$503F
$6000–$603F
$7000–$703F
$8000–$803F
$9000–$903F
$A000–$A03F
$B000–$B03F
$C000–$C03F
$D000–$D03F
$E000–$E03F
$F000–$F03F
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
4-9
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