MC68HC711D3CFNE2 Datasheet, PDF (64/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
DDRB — Data Direction Register for Port B
RESET:
Bit 7
DDB7
0
6
DDB6
0
5
DDB5
0
4
DDC4
0
3
DDB3
0
2
DDB2
0
DDB[7:0] — Data Direction for Port B
0 = Corresponding port B pin configured for input only
1 = Corresponding port B pin configured as output
1
DDB1
0
$0006
Bit 0
DDB0
0
6.3 Port C
Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-
tiplexed mode, port C pins are configured as multiplexed address/data pins. During the
data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.
PORTC — Port C Data
S. Chip
or Boot:
RESET:
Expan.
or Test:
RESET:
Bit 7
PC7
PC7
ADDR7/
DATA7
6
5
4
3
2
1
PC6
PC5
PC4
PC3
PC2
PC1
PC6
PC5
PC4
PC3
PC2
PC1
Reset configures pins as HiZ inputs
ADDR6/
DATA6
ADDR5/
DATA5
ADDR4/
DATA4
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
Reset configures pins as multiplexed, low-order address/data I/O
DDRC — Data Direction Register for Port C
RESET:
Bit 7
DDC7
0
6
DDC6
0
5
DDC5
0
4
DDC4
0
3
DDC3
0
2
DDC2
0
1
DDC1
0
DDC[7:0] — Data Direction for Port C
0 = Input
1 = Output
$0003
Bit 0
PC0
PC0
ADDR0/
DATA0
$0007
Bit 0
DDC0
0
6.4 Port D
The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and
SPI subsystems, or for bus data direction control. Port D can be read at any time. In-
puts return the sensed levels at the pin; outputs return the input level of the port D pin
drivers. If port D is written, the data is stored in an internal latch, and can be driven only
if port D is configured for general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow
on the bus in expanded and special test modes.
PARALLEL I/O
6-2
TECHNICAL DATA
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