MC68HC711D3CFNE2 Datasheet, PDF (68/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
(WRITE ONLY)
10 (11) - BIT Tx SHIFT REGISTER
H (8) 7 6 5 4 3 2 1 0 L
DDD1
PIN BUFFER
PD1
AND CONTROL
TxD
8
SCCR1 SCI CONTROL 1
TRANSMITTER
CONTROL LOGIC
FORCE PIN
DIRECTION (OUT)
8
SCSRINTERRUPT STATUS
8
TDRE
TIE
TC
TCIE
SCCR2 SCI CONTROL 2
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 7-1 SCI Transmitter Block Diagram
11 SCI TX BLOCK
7.3 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register
receives data and transfers it to a parallel receive data register (SCDR) as a complete
word. Refer to Figure 7-2. This double buffered operation allows a character to be
shifted in serially while another character is already in the SCDR. An advanced data
SERIAL COMMUNICATIONS INTERFACE
7-2
TECHNICAL DATA
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