MC68HC711D3CFNE2 Datasheet, PDF (7/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

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Freescale Semiconductor, Inc.
LIST OF ILLUSTRATIONS
Title
Page
1-1 MC68HC11D3 Block Diagram ........................................................................ 1-2
2-1 Pin Assignments for 44-Pin PLCC ................................................................. 2-1
2-2 Pin Assignments for 40-Pin DIP ..................................................................... 2-2
2-3 External Reset Circuit ..................................................................................... 2-3
2-4 Common Crystal Connections ........................................................................ 2-3
2-5 External Oscillator Connections ..................................................................... 2-4
2-6 One Crystal Driving Two MCUs ..................................................................... 2-4
3-1 Programming Model ....................................................................................... 3-1
3-2 Stacking Operations ....................................................................................... 3-3
4-1 Address/Data Demultiplexing ......................................................................... 4-2
4-2 MC68HC11D3 Memory Map .......................................................................... 4-3
4-3 RAM Standby MODB/V_STBY Connections ...................................................... 4-6
5-1 Processing Flow out of Reset (1 of 2) .......................................................... 5-12
5-2 Interrupt Priority Resolution (1 of 2) ............................................................. 5-14
5-3 Interrupt Source Resolution within SCI ........................................................ 5-16
7-1 SCI Transmitter Block Diagram ...................................................................... 7-2
7-2 SCI Receiver Block Diagram .......................................................................... 7-3
7-3 SCI Baud Rate Diagram ............................................................................... 7-10
7-4 Interrupt Source Resolution within SCI ........................................................ 7-12
8-1 SPI Block Diagram ......................................................................................... 8-2
8-2 SPI Transfer Format ....................................................................................... 8-3
9-1 Timer Clock Divider Chains ............................................................................ 9-2
9-2 Capture/Compare Block Diagram .................................................................. 9-4
9-3 Pulse Accumulator ....................................................................................... 9-16
A-1 Test Methods .................................................................................................. A-3
A-2 Timer Inputs ................................................................................................... A-4
A-3 POR and External Reset Timing Diagram ...................................................... A-5
A-4 STOP Recovery Timing Diagram ................................................................... A-6
A-5 WAIT Recovery Timing Diagram .................................................................... A-7
A-6 Port Write Timing Diagram ............................................................................. A-8
A-7 Port Read Timing Diagram ............................................................................. A-8
A-8 Multiplexed Expansion Bus Timing Diagram ................................................ A-10
A-9 SPI Master Timing (CPHA = 0) .................................................................... A-12
MC68HC11D3
TA
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