MC68HC711D3CFNE2 Datasheet, PDF (100/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
TFLG2 — Timer Interrupt Flag 2
Bit 7
6
5
4
3
2
TOF
RTIF
PAOVF
PAIF
0
0
RESET:
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
$0025
1
Bit 0
0
0
0
0
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.6 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.6 Pulse Accumulator.
Bits [3:0] — Not implemented
Always read zero
9.4.2 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the real-time interrupt system. Bit
DDRA3 determines whether Port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
PACTL — Pulse Accumulator Control
RESET:
Bit 7
DDRA7
0
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
DDRA3
0
2
I4/O5
0
DDRA7 — Data Direction Control for Port A Bit 7
Refer to 9.6 Pulse Accumulator.
PAEN — Pulse Accumulator System Enable
Refer to 9.6 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode
Refer to 9.6 Pulse Accumulator.
PEDGE — Pulse Accumulator Edge Control
Refer to 9.6 Pulse Accumulator.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to SECTION 6 PARALLEL I/O.
I4/O5 — Input Capture 4/Output Compare 5
Refer to 9.2 Input Capture.
1
RTR1
0
$0026
Bit 0
RTR0
0
9-14
TIMING SYSTEM
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TECHNICAL DATA