MC68HC711D3CFNE2 Datasheet, PDF (60/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
BEGIN
FLAG
Y
RDRF = 1?
N
Y
OR = 1?
N
Y
RIE = 1?
N
Y
RE = 1?
N
Y
TDRE = 1?
N
Y
TIE = 1?
N
Y
TE = 1?
N
Y
TC = 1?
N
Y
TCIE = 1?
N
Y
IDLE = 1?
N
Y
ILIE = 1?
N
Y
RE = 1?
N
NO
VALID SCI REQUEST
VALID SCI REQUEST
INT SOURCE RES
Figure 5-3 Interrupt Source Resolution within SCI
5.5 Low-Power Operation
Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The
WAIT condition suspends processing and reduces power consumption to an interme-
diate level. The STOP condition turns off all on-chip clocks and reduces power con-
sumption to an absolute minimum while retaining the contents of all 192 bytes of RAM.
5.5.1 WAIT
The WAI opcode places the MCU in the WAIT condition, during which the CPU regis-
ters are stacked and CPU processing is suspended until a qualified interrupt is detect-
ed. The interrupt can be an external IRQ, an XIRQ, or any of the internally generated
interrupts, such as the timer or serial interrupts. The on-chip crystal oscillator remains
active throughout the WAIT standby period.
The reduction of power in the WAIT condition depends on how many internal clock sig-
5-16
RESETS AND INTERRUPTS
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Go to: www.freescale.com
TECHNICAL DATA