MC68HC711D3CFNE2 Datasheet, PDF (108/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table A-4 Control Timing
Characteristic
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min Max Min Max Min Max
Frequency of Operation
f_o
dc 1.0 dc 2.0 dc 3.0 MHz
E-Clock Period
t_cyc
1000 — 500 — 333 —
ns
Crystal Frequency
f_XTAL
— 4.0 — 8.0 — 12.0 MHz
External Oscillator Frequency
4 f_o
dc 4.0 dc 8.0 dc 12.0 MHz
Processor Control SetupTime
t_PCSU = 1/4 t_cyc + 50 ns
t_PCSU
300 — 175 — 133 —
ns
Reset Input Pulse Width
PW_RSTL
To Guarantee External Reset Vector
8
—
8
—
8
—
t_cyc
Minimum Input Time
1
—
1
—
1
—
t_cyc
(Can Be Preempted by Internal Reset)
Mode Programming Setup Time
Mode Programming Hold Time
Interrupt Pulse Width,
IRQ Edge-Sensitive Mode
PW_IRQ = t_cyc + 20 ns
Wait Recovery Startup Time
Timer Pulse Width,
Input Capture Pulse
Accumulator Input
PW_TIM = t_cyc + 20 ns
t_MPS
2
—
2
—
2
—
t_cyc
t_MPH
10 — 10 — 10 —
ns
PW_IRQ 1020 — 520 — 353 —
ns
t_WRS
—
4
—
4
—
4
t_cyc
PW_TIM 1020 — 520 — 353 —
ns
NOTES:
1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
2. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
PA[2:0] ¹
PA[2:0] ²
PA7 ^1,3
PA7 ^2,3
PW_TIM
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure A-2 Timer Inputs
TIMER INPUTS TIM
ELECTRICAL CHARACTERISTICS
A-4
TECHNICAL DATA
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