MC68HC711D3CFNE2 Datasheet, PDF (65/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
PORTD — Port D Data
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
0
0
0
0
0
0
0
0
Alt. Func.: R/W
AS
SCK
MOSI
MISO
TxD
RxD
DDRD — Data Direction Register for Port D
RESET:
Bit 7
DDD7
0
6
DDD6
0
5
DDD5
0
4
DDD4
0
3
DDD3
0
2
DDD2
0
1
DDD1
0
$0009
Bit 0
DDD0
0
DDD[7:0] — Data Direction for Port D
When port D is a general-purpose I/O port, the DDRD register controls the direction of
the I/O pins as follows:
0 = Configures the corresponding port D pin for input
1 = Configures the corresponding port D pin for output
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W outputs.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave
select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master
mode, DDD5 affects port D bit 5 as follows:
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be
inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI
expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3,
and 4 are set.
PACTL — Pulse Accumulator Control
$0026
RESET:
Bit 7
DDRA7
0
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
DDRA3
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
DDRA7 — Data Direction Control for Port A Bit 7
Refer to SECTION 9 TIMING SYSTEM.
PAEN — Pulse Accumulator System Enable
Refer to SECTION 9 TIMING SYSTEM.
PAMOD — Pulse Accumulator Mode
Refer to SECTION 9 TIMING SYSTEM.
PEDGE — Pulse Accumulator Edge Control
Refer to SECTION 9 TIMING SYSTEM.
DDRA3 — Data Direction for Port A Bit 3
Overridden if an output compare function is configured to control the PA3 pin.
0 = Input only
1 = Output
PARALLEL I/O
TECHNICAL DATA
6-3
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