MC68HC711D3CFNE2 Datasheet, PDF (112/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table A-5 Peripheral Port Timing
Characteristic
Frequency of Operation (E-Clock Frequency)
E-Clock Period
Peripheral Data Setup Time
MCU Read of Ports A, B, C, and D
Peripheral Data Hold Time
MCU Read of Ports A, B, C, and D
Delay Time, Peripheral Data Write
Symbol
f_o
t_cyc
t_PDSU
1.0 MHz
Min Max
dc 1.0
1000 —
100 —
2.0 MHz
Min Max
dc 2.0
500 —
100 —
3.0 MHz
Min Max
dc 3.0
333 —
100 —
Unit
MHz
ns
ns
t_PDH
50 — 50
—
50 — ns
t_PWD
MCU Write to Port A
MCU Writes to Ports B, C, and D
t_PWD = 1/4 t_cyc + 150 ns
— 200 — 200 — 200 ns
— 350 — 225 — 183 ns
NOTES:
1. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respec-
tively).
2. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
MCU WRITE TO PORT
E
PORTS
B, C, D
PORT A
PREVIOUS PORT DATA
t _PWD
PREVIOUS PORT DATA
NEW DATA VALID
tPWD
NEW DATA VALID
D3 PORT WRITE TIM
Figure A-6 Port Write Timing Diagram
E
PORTS
A, B, C, D
MCU READ OF PORT
tPDSU
tPDH
Figure A-7 Port Read Timing Diagram
D3 PORT READ TIM
ELECTRICAL CHARACTERISTICS
A-8
TECHNICAL DATA
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